A three-dimensional integrated circuit (3D-IC) memory technique has been developed to increase memory capacity of a semiconductor memory device. The 3D-IC memory technique includes a variety of methods for arranging memory cells three-dimensionally. In addition to the 3D-IC memory technique, a patterning technique for fine patterns and a multi-level cell (MLC) technique may be used to increase the memory capacity of the semiconductor memory device. However, the patterning technique for the fine patterns may be very expensive, and the MLC technique may not be suitable for increasing the number of bits per unit cell. Thus, the 3D-IC memory technique may be important to increasing the memory capacity. In addition, if the patterning technique for the fine patterns and the MLC technique are combined with the 3D-IC memory technique, the memory capacity may further increase. Thus, the patterning technique for the fine patterns and the MLC technique may be developed independently of the 3D-IC memory technique.